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DesignCon 2024
DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
How can you create the best AI infrastructure? Let Keysight enable you to push the boundaries of engineering by solving complex design, emulation, and test challenges to create and deliver the best AI infrastructure and experiences to your customers.
DATE
January 30 – February 1, 2024
LOCATION
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, CA 95054
Floor map
Showcase Demos
1.6T 212G PHY Rx
Featuring Keysight’s solution to test and validate next-generation SerDes designs running at 212 Gbps per lane is a key technology for high-performance computing to fully unleash the potential of AI. The demo will focus on receiver testing.
1.6T 212G PHY Tx
Featuring Keysight’s solution to test and validate next-generation serializer / deserializer (SerDes) designs running at 212 Gbps per lane is a key technology for high-performance computing to fully unleash the potential of AI. The demo will focus on transmitter testing.
DDR5 simulation and test
Next-generation memory designs need lower noise and reduced loading to report design performance accurately. Memory designs that require testing both Tx and Rx can now push the limits of memory test solutions with higher bandwidth probing and more efficient design to test workflow.
Enable PCIe® 7.0 Technology
Featuring the Keysight PCI Express® 7.0 transmitter and receiver test solutions and test automation software to enable early pathfinding and accelerated delivery of your Gen 7 silicon to the market.
Signal Integrity PLTS
This demo showcases the importance of signal integrity in high-speed digital designs using a Keysight vector network analyzer and time domain reflectometer for calibration, measurement, and post-measurement processing.
USB4 V2.0 PHY IP Operating at 80Gbps
This workstation presents Keysight's test solution for USB4 transmitter, receiver, and return loss. It also showcases Keysight test automation software featuring measurement acceleration technology to provide the fastest results in the market.
EDA Chiplet PHY Designer
Showcasing the new Keysight chiplet physical layer (PHY) designer, which enables you to model, simulate, and analyze the high-speed channel between two D2D PHY interfaces used for interconnecting two chiplets.
PCIe 6.0® and CXL 2.0 Protocol
Featuring the new Keysight P5570A PCIe® 6.0 analyzer and Keysight P5573A PCIe® 6.0 exerciser that debugs PCIe 6.0 protocol traffic on a real Gen 6 link using advanced triggers and filters while emulating both root complex and endpoint scenarios.
Keysight Education Forum (KEF)
Ballroom K
Wednesday, January 31 Sessions
8:00 a.m. – 8:45 a.m.
How material properties can make or break your data center performance
9:00 a.m. – 9:45 a.m.
Navigating the challenges of testing USB at 80Gbps
11:00 a.m. – 11:45 p.m.
The road to PCIe 7.0: Advanced testing challenges at 32GBaud PAM4
LUNCH
1:00 p.m. – 1:45 p.m.
Optimizing UCIe Implementations in Multi-Die High-Speed Digital Designs
2:00 p.m. – 2:45 p.m.
112G Linear low power electro / optic physical layer
3:00 p.m. – 3:45 p.m.
Emerging data-center 1.6Tbps electro / optic validation at 224Gbps
Conference Papers by Keysight
| Date | Event Type | Time | Room | Topic |
|---|---|---|---|---|
| January 30 | Tutorial | 2:00 p.m. - 4:30 p.m. | Ballroom A | Latest measurement techniques for next-generation memory system |
| January 30 | Panel | 4:45 p.m. - 6:00 p.m. | Ballroom E | Panel case of the closing eye |
| January 31 | Panel | 4:45 p.m. - 6:00 p.m. | Ballroom G | Test on Wheels Panel: T&M for automotive standards |
| January 31 | Technical Session | 8:00 a.m. - 8:45 a.m. |
Ballroom A | A practical review of IBIS DDRS enhancements |
| January 31 | Technical Session | 8:00 a.m. - 8:45 p.m. |
Ballroom D | Using measured waveform data in AMI simulation for system design |
| January 31 | Technical Session | 9:00 a.m. - 9:45 a.m. | Ballroom C | Design, simulation, and validation challenges of a scalable 2000 Amp core power rail |
| January 31 | Technical Session | 12:15 p.m. - 1:00 p.m. |
Ballroom C | 200 Gbps signaling per electrical land over 1 meter of twin-axial copper cable |
| January 31 | Theater Session | 1:15 p.m. - 2:00 p.m. |
Chiphead Theatre | Hands-On PDN impedance and calibration basics |
| January 31 | Technical Session | 2:00 p.m. - 2:45 p.m. |
Ballroom C | 800G Linear Direct Drive network system design and implementation |
| January 31 | Panel | 4:00 p.m. - 5:15 p.m. |
Ballroom C | PCle and PAM4: Pathway to 128GT/s and interoperability at 64GT/s |
| January 31 | Panel | 4:00 p.m. - 5:15 p.m. |
Ballroom F | OIF Update on 224 Gbps Common Electrical Interfaces (CEI) Development |
| February 1 |
Technical Session | 2:00 p.m. - 2:45 p.m. |
Ballroom B | Pam4 Signal Testing Considerations: Learnings from PCle & Ethernet/OIF-CEI for 100+ Gbps per lane |
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